1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an ESD protective circuit for enhancing tolerance to electrostatic discharge breakdown and its manufacturing method.
2. Description of the Related Art
As an ESD protective circuit for enhancing tolerance to an electrostatic discharge (ESD) breakdown in a semiconductor device, an ESD protective circuit shown in FIG. 1 of Japanese unexamined patent application publication No. 2004-15003 is used. This ESD protective circuit includes an NMOS transistor (hereinafter called transistor) having the source electrode connected to a grounding potential and the drain electrode connected to a fetch terminal. The voltage surge applied to the fetch terminal is discharged to the grounding potential by way of a lateral bipolar transistor parasitizing in this transistor.
To cope with discharge current of large voltage surge, an ESD protective circuit having a finger structure shown in FIG. 4 and FIG. 5 of Japanese unexamined patent application publication No. 2004-15003 is devised. In this ESD protective circuit, a plurality of transistors is connected in parallel. Since the discharge current can be divided and distributed into transistors, large discharge current of voltage surge can be released. In each transistor, a ballast resistance is connected in series. This ballast resistance is used in the ESD protective circuit of the finger structure for the purpose of preventing other transistors from failing to conduct when one transistor conducts to lower the voltage of the fetch terminal.
FIG. 1 of Japanese unexamined patent application publication No. 2002-134630 discloses a layout structure of a semiconductor device including such ballast resistance. This semiconductor device comprises a high concentration impurity diffusion layer 29 (drain electrode), a high concentration impurity diffusion layer for fetch 29e (signal fetch terminal), and a protective resistance region 31 enclosed by them. On the surface of the high concentration impurity diffusion layer 29 and high concentration impurity diffusion layer for fetch 29e, a metal silicide layer 33 is formed. On the other hand, on the surface of the protective resistance region 31, a mask layer 28 formed of silicon nitride film is formed. Accordingly, between the high concentration impurity diffusion layer 29 and high concentration impurity diffusion layer for fetch 29e, the metal silicide layer 33 is cut off on the surface of the protective resistance region 31. Therefore, the high concentration impurity diffusion layer 29 and high concentration impurity diffusion layer for fetch 29e are connected electrically only by way of the protective resistance region 31, they can be connected at high resistance.